位置：成果数据库 > 会议 > 会议详情页
A new efficient method for characterizing time constants of switching oxide traps
  • 所属机构名称：北京大学
  • 会议名称：52nd IEEE International Reliability Physics Symposium, IRPS 2014
  • 时间：2014
  • 成果类型：会议
  • 相关项目：新型围栅硅纳米线MOS器件的涨落性与可靠性研究
作者： Guo, Shaofeng|Ren, Pengpeng|Wang, Runsheng|Yu, Zhuoqing|Luo, Mulong|Zhang, Xing|Huang, Ru|
同会议论文项目
新型围栅硅纳米线MOS器件的涨落性与可靠性研究
期刊论文 8 会议论文 20
同项目会议论文
Investigations on the Correlation between Line-edge-roughness (LER) and Line-width-roughness (LWR) i
New observations on complex RTN in scaled high-κ/metal-gate MOSFETs - The role of defect coupling un
Performance Investigation of SRAM Cells Based on Gate-all-around (GAA) Si Nanowire Transistor for Ul
Two-dimensional Self-limiting Oxidation for Non-planar Silicon Nano-devices from Top-down Approach:
Impacts of cycle-to-cycle variation effects on the prediction of NBTI degradation and the resulted d
Improving Analog/RF Performance of Multi-gate Devices through Multi-dimensional Design Optimization
New Observations on AC NBTI induced Dynamic Variability in Scaled High-κ/Metal-gate MOSFET
New observations on the AC random telegraph noise (AC RTN) in nano-MOSFETs
Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits
Simulation of correlated line-edge roughness in multi-gate devices
On the statistical trap-response (STR) method for characterizing random trap occupancy and NBTI fluc
On the AC Random Telegraph Noise (RTN) in MOS Devices: An Improved Multi-phonon based Model
Experimental Study on the Variation of NBTI Degradation in Nano-scaled High-k/Metal-gate PFETs
New Understanding on the Single-Trap Response under NBTI Stress and the Resulted Stochastic Degradat
Investigations on the gate oxide dependence of AC RTN characteristics in nanoscaled MOSFETs: SiON vs
Deep understanding of AC RTN in MuGFETs through new characterization method and impacts on logic cir
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis
New insights into AC RTN in scaled high-κ/ metal-gate MOSFETs under digital circuit operations
A Unified Approach for Trap-Aware Device/Circuit Co-Design in Nanoscale CMOS Technology