位置：成果数据库 > 会议 > 会议详情页
A novel floating-point function unit combining MAF and 3-input adder
  • 所属机构名称：西北工业大学
  • 会议名称：2012 2nd IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 20
  • 时间：2012
  • 成果类型：会议
  • 相关项目：基于虚拟机的微体系结构级仿真原型快速构造方法研究
作者： Yao, Tao|Gao, Deyuan|Ren, Xianglong|Han, Limin|Fan, Xiaoya|Yang, Lei|
同会议论文项目
基于虚拟机的微体系结构级仿真原型快速构造方法研究
期刊论文 16 会议论文 21 专利 2 著作 1
同项目会议论文
Adaptive Low-Power Transmission Coding for Serial links in network-on-chip
A fast virtual device framework for improving RTL verification efficiency
Design of a high reliable SOC
Functional verification flow for an embedded microprocessor
A multi-path fused add-subtract unit for digital signal processing
Three-operand floating-point adder
Logic simulation acceleration based on GPU
A VMM/FPGA co-verification method for “ Longtium Stream ” processor
Backplane bus controller implementation in Fpga for hard real time control systems
Global prefetcher aggressiveness control for chip-multiprocessor
Performance evaluation of a massively parallel decoder for CISC microprocessors
Interconnection design of Longteng M2 quad-core processor
Implementation of data transfer and synchronous pulse operation for ARINC 659
Study on curriculum design of system on chip
FPGA based real time implementation scheme for ARINC 659 backplane data bus
Dual-Path Architecture of Floating-Point Dot Product Computation
A survey on cache coherence for tiled many-core processor
The design of host interface unit in ARINC659 bus control chip
Channel allocation for low-power NoC design based on Improved Asymmetric Multi-Channel router
Modeling and performance analysis of network on chip based on improved asymmetric multi-channel rout