欢迎您!
东篱公司
退出
申报数据库
申报指南
立项数据库
成果数据库
期刊论文
会议论文
著 作
专 利
项目获奖数据库
位置:
成果数据库
>
会议
> 会议详情页
An on-chip test clock control scheme for multi-clock at-speed testing
所属机构名称:中国科学院计算技术研究所
会议名称:16th Asian Test Symposium, ATS 2007
成果类型:会议
会场:Beijing, China
相关项目:面向串扰的时延测试
作者:
Fan, Xiaoxin|Wang, Laung-Terng|Hu, Yu|
同会议论文项目
面向串扰的时延测试
期刊论文 19
会议论文 13
专利 3
同项目会议论文
A case study on at-speed testing of a gigahertz microprocessor
Codeword selection for crosstalk avoidance and error correction on interconnects
Static crosstalk noise analysis with transition map
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topolog
Adaptive diagnostic pattern generation for scan chains
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit fa
Reliable network-on-chip router for crosstalk and soft error tolerance
The design-for-testability features of a general purpose microprocessor
Test generation for crosstalk glitches considering multiple coupling effects
Flip-flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan
Test Pattern Selection for Small-Delay Defects Considering Hazards
Multiple coupling effects oriented path delay test generation