位置：成果数据库 > 会议 > 会议详情页
Power-Aware Software Prefetching
  • 所属机构名称：中国人民解放军国防科学技术大学
  • 成果类型：会议
  • 相关项目：高效能并行计算机体系结构研究
同会议论文项目
高效能并行计算机体系结构研究
期刊论文 72 会议论文 39 获奖 3
同项目会议论文
Implementation of Rotation Invariant Multi-View Face Detection on FPGA
FPGA-Accelerated Molecular Dynamics Simulations: An Overview
Power-Directed Software Prefetching Algorithm with Dynamic Voltage Scaling
A 64-bit stream processor architecture for scientific applications
FPGA Accelerating Double/Quad-Double High Precision Floating-Point Applications for ExaScale Computi
FIDP:A Novel Architecture for Lifting-Based 2D DWT in JPEG2000
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
Impact of Loop Unrolling on Area, Throughput and Clock Frequency for Window Operations based on a Da
Area and Throughput Trade-offs in Design of Arithmetic Encoder for JPEG2000
Architecture-Based Optimization for Mapping Scientific Applications to Imagine
Multi-access memory architecture for image applications with multiple interested regions
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA
Window Memory Accesses Method in Alternate Row/Column Matrix Access Systems
FPGA Accelerating Three QR Decomposition Algorithms in the Uinfied Pipelined Framework
FPGA-Based Memory-Efficient Parallel RNA Secondary Structure Prediction Accelerator Using SCFGs
Designing and Analysizing BOIN – A Novel On-Chip Optical Interconnection Network
Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs
DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor
Design and synthesis of a high-speed hardware linked-list for digital image processing
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware
FPGA SAR Processor with Window Memory Accesses
FPGA-Accelerated Active Shape Model for Real-Time People Tracking
Blocking LU decomposition for FPGAs
Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Exte
Implementation and Optimization of Sparse Matrix-Vector Multiplication on Imagine Stream Processor
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
BOIN: A Novel Bufferless Optical Interconnection Network for High Performance Computer
Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA
Fine-grained Parallel Application Specific Computing for RNA Secondary Structure Prediction on FPGA
Fine-grained Parallel Zuker Algorithm Accelerator with Storage Optimization on FPGA
Fine-grained Parallel Application Specific Computing for RNA Secondary Structure Prediction Using SC
FPGA accelerating algorithms of active shape model in people tracking applications
Rectangularly multi-module memory system with table-based dynamic addressing scheme
Computation rotating for data reuse