位置：成果数据库 > 会议 > 会议详情页
On Handling of Incremental Floorplanning for 3D ICs
  • 所属机构名称：清华大学
  • 会议名称：10th Joint Conference on Information Sciences, JCIS 2007
  • 成果类型：会议
  • 相关项目：面向时序设计的布图规划算法研究
作者： Xianlong Hong|Yuchun Ma|Xin Li|
同会议论文项目
面向时序设计的布图规划算法研究
期刊论文 2 会议论文 34 获奖 1 专利 2
同项目会议论文
PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource
PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning
Interconnect Power Optimization Based on Timing Analysis
Congestion - driven Floorplanning based on Two-stage Optimization
Multi-objective Floorplanning Based On Fuzzy Logic
Modern floorplanning with boundary clustering constraint
Simultaneous buffer and interlayer via planning for 3D floorplanning
A novel thermal optimization flow using incremental floor planning for 3D ICs
Incremental power optimization for multiple supply voltage design
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization
An efficient thermal optimization flow using incremental floorplanning for 3D microprocessors
An efficient thermal optimization flow using incremental floorplanning for 3D microprocessors
Floorplan and Power/Ground network co-design using guided incremental floorplanning
Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design
A Fast 3D-BSG Algorithm for 3D Packing Problem
An Analytical Approach to Incremental Floorplanning
Thermal-aware incremental floorplanning for 3D ICs
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circu
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
An accurate and efficient probabilistic congestion estimation model in x architecture
Hierarchical thermal model using Gauss-Seidel method in floorplanning
An Effective Buffer Planning Algorithm for IP Based Fixed-Outline SOC Placement
An Effective Buffer Planning Algorithm for IP Based Fixed-Outline SOC Placement
Simultaneous optimization of performance and thermal effects based on two-stage microarchitectural f
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
Fine grain 3D integration for microarchitecture design through cube packing exploration
Fine grain 3D integration for microarchitecture design through cube packing exploration
Voltage island aware incremental floorplanning algorithm based on MILP formulation
Design space exploration for 3D integrated circuits
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs