欢迎您!
东篱公司
退出
申报数据库
申报指南
立项数据库
成果数据库
期刊论文
会议论文
著 作
专 利
项目获奖数据库
位置:
成果数据库
>
会议
> 会议详情页
Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differentia
所属机构名称:复旦大学
成果类型:会议
相关项目:安全芯片旁道攻击方法及其防御技术研究
同会议论文项目
安全芯片旁道攻击方法及其防御技术研究
期刊论文 26
会议论文 20
同项目会议论文
Very Low-cost VLSI Implementation of AES Algorithm
Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation
A Low-Cost Cryptographic Processor for Security Embedded System
A New Dual-Field Elliptic Curve Cryptography Processor
应用于安全处理器的RSA/SHA复用加密单元设计
A New Low Cost and Reconfigurable RSA Crypto-Processor
A Reconfigurable and Ultra Low-cost VLSI Implementation of SHA-1 and MD5 function
A Scalable Design of RSA Crypto-coprocessor
A VLSI implementation of ECC combined with AES
Differential Power Analysis and Differential Fault Attack Resistant AES Algorithm and its VLSI Imple
VLSI Implementation of an AES Algorithm Resistant to Differential Power Analysis Attack
一种面向无线安全的双核SOC平台
A Low-cost and High-performance SOC Design for OMA DRM2 Applications
A Modified High-Radix Scalable Montgomery Multiplier
Design and VLSI Implementation of a Security ASIP
A High-Performance Platform-Based SOC for Information Security
A Full-custom Design of AES SubByte Module with Signal Independent Power Consumption
Core-based Multi-function Security Processor with GALS Wrapper
A Programmable Security Processor for Cryptography Algorithms