位置：成果数据库 > 会议 > 会议详情页
Private Cache Partitioning: A Method to Reduce the Off-chip Missrate Of Concurrently Executing Appli
  • 所属机构名称：中国人民解放军国防科学技术大学
  • 会议名称：2011 International Conference on System Engineering and Modeling
  • 时间：2011.3.3
  • 成果类型：会议
  • 相关项目：多核多线程DSP适应性存储结构研究
作者： Lihao, Xie Lunguo, Liutao, Liu Guanghui|
同会议论文项目
多核多线程DSP适应性存储结构研究
期刊论文 23 会议论文 9 专利 7
同项目会议论文
A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors
architectural implications for SIMD processors in the wireless communication Domain
Customized MMRF: Efficient Matrix Operations on SIMD Processors
Design and Chip Implementation of a Heterogeneous Multicore DSP
Optimal Memory Time Partitioning: Improve the Overall Performance of Concurrently Executing Applicat
A Multi-Time Sharing Scheme in Optimal Memory Time Partitioning for Chip-Multiprocessors
Understanding How Memory-Level Parallelism Affects the Processors Performance
How Many Entries We Need in Miss Handling Architectures