位置：成果数据库 > 会议 > 会议详情页
Cost Effective Soft Error Mitigation for Parallel Adders by Exploiting Inherent Redundancy
  • 所属机构名称：中国人民解放军国防科学技术大学
  • 会议名称：2010 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
  • 成果类型：会议
  • 相关项目：先进微处理器软错误易感性动态预测和免疫技术研究
作者： Yan Sun|Minxuan Zhang|Shaoqing Li|Yali Zhao|
同会议论文项目
先进微处理器软错误易感性动态预测和免疫技术研究
期刊论文 30 会议论文 14
同项目会议论文
FAST: A Framework of Accurate SER-Estimation at Transistor-Level for Logic Circuits
RC-Cache: Soft Error Mitigation Techniques for Low-Leakage On-Chip Caches
Towards Online Application Cache Behaviors Identification in CMPs
Phase Characterization and Classification for Micro-architecture Soft Error
Characterizing Time-Varying Behavior and Predictability of Cache AVF
Accurate vulnerability estimation for cache hierarchy
Evaluation of deflection routing on various NoC topologies
Exploiting Idle Resources for Reducing SER of Microprocessor Functional Units
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Pytho
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip
Partitioning mechanism based on dynamic Allocation of Data entries for chip multiprocessors
An Efficient Hardware Random Number Generator Based on the MT Method
高性能处理器中ECC纠错码的设计及实现