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Power-balanced Delay-Insensiti
  • 所属机构名称：清华大学
  • 成果类型：会议
  • 相关项目：SOC设计的关键技术研究及传导语音SOC实现
同会议论文项目
SOC设计的关键技术研究及传导语音SOC实现
期刊论文 93 会议论文 76 著作 3
同项目会议论文
Universal data model platform
Parameterized Function Unit Li
Model Checking of Microprocess
基于WDFG模型的专用指令集自动生
基于THUASDSP2004的H.263编解码
高层次综合中低功耗算法研究
STUDY ON HNR IN TRANSMITTED SO
一种可编程数字信号处理器的设计
A New Methodology of Integrati
On-Chip Network Evolution Usin
A Scalable Architecture of Hig
Model Checking of A DLX Microp
RTL验证中的混合可满足性求解
集成电路芯片瞬时功耗测量-分析
用硬件验证语言实现模拟验证方法
采用CLP进行高层设计的性质检验
An Improved Sawtooth Oscillato
An Improved DMA Controller for
Cooperative Bounded Model Chec
Hierarchical Property Checking
AGOM: A Novel System Level Des
Integrated Hardware/Software P
A Component Library For IP Cor
Hazard Free Sawtooth Oscillato
Design of Data-Path for A VLIW
VS-ISA: A Video Specific Instr
Interconnect Delay Optimizatio
Bounded Model Checking for RTL
Optimization Techniques in a F
A low power side-channel attac
CA-Ex: A Tuning-Incremental Me
A Scaleable DSP System for ASI
SLCAO: An Effective System Lev
Sub-Block Oriented Media Proce
基于可满足性问题求的时序电路性
Fast and Efficiently Binding o
BTSAT：A Hybrid Satisfiability
Implementation Method about Ve
Piss: A Performance-Driven Int
Floating-Point Unit Processing
Automated analog circuits symm
ACSAT: A SAT Solver via Solvin
An Integrated CAD Tool for ASI
A Retargetable Compiler of VLI
AL/RTL Co-Modeling And General
Circuit Design and Verificatio
Extend Force-directed Scheduli
Cooperation of SMV and Jeda fo
Interconnect Power Optimizatio
Epistasis Reducing through Con
Interconnect Delay Optimizatio
Systematic Method to Synthesiz
TESTLINE: An IEEE P1500 Compat
A New Methodology of Integrati
Safety Checking by Problem Sol
A Distributed Architecture Mod
A Fast Algorithm for Power Opt
PFGASAT-a Genetic SAT Solver C
System-level Architectural Exp
Partition-based Retiming and P
Further Minimization of Bdds f
Extraction of Feedback Informa
A Congestion Driven Re-Synthes
Circuit Design and Verificatio
Power optimization in data-pat
Multiply-Add Fused Float Point
A New Register File Access Arc
CGEM: A Communication Graph Ex
A Novel Method of Generating T
High Level Synthesis with Mult
From Software to Hardware: A N
A Novel Algorithm for Common S
A Heterogeneous Dependency Gra
iTuCoMe: HCDFG-based Increment
VLSI Implementation of a Decim