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SimICT: A Fast and Flexible Framework for Performance and Power Evaluation of Large-Scale Architectu
  • 所属机构名称：中国科学院计算技术研究所
  • 会议名称：International Symposium on Low Power Electronics and Desig(ISLPED)
  • 时间：2013.9.4
  • 成果类型：会议
  • 相关项目：超并行高效能计算机体系结构与设计方法研究
同会议论文项目
超并行高效能计算机体系结构与设计方法研究
期刊论文 124 会议论文 114
同项目会议论文
Scattered Superpage: A Case for Bridging the Gap between Superpage and Page Coloring
A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture
Effective fault localization based on minimum debugging frontier set
RISO: Relaxed Network-on-Chip Isolation for Cloud Processors
RSAK: Random Stream AttacK for Phase Change Memory in Video Applications
HRUL: A Hardware Assisted Recorder for User-level Application
Low Power Cache Architecture with Hybird Approach of Filtering Unnecessary Way Accesses
HHC：Hierarchical Hardware Checkpointing to Accelerate Fault Recovery for SRAM-based FPGAs
SpontaneousReload Cache --- Mimicking a Larger Cache with Minimal Hardware Requirement
Diagnosis and Layout Aware (DLA) Scan Chain Stitching
Orchestrator: a Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded applications
Modeling Two Orthogonal Ways to Hunt on Heterogeneous Many-cores
Capturing Post-Silicon Variation by Layout-Aware Path-Delay Testing
SmartCap: user experience-oriented power adaptation for smartphone's application processor
DCNSim: A Unified and Cross-layer Computer Architecture Simulation Framework for Data Center Network
SMAT: an input adaptive auto-tuner for sparse matrix-vector multiplication
Reproducing Concurrency Bugs Using Local Clocks
Flexible Sparse Directories Utilizing Multi-Level Memristors
DTail: a flexible approach to DRAM refresh management.
DWC: dynamic write consolidation for phase change memory systems.
Truthful Strategy and Resource Integration for Multi-tenant Data Center Demand Response
Oblivious Integral Routing for Minimizing the Quadratic Polynomial Cost
Fuel Cell Generation in Geo-Distributed Cloud Services: A Quantitative Study
HSPT: Practical Implementation and Efficient Management of Embedded Shadow Page Tables for Cross-ISA
Manfred Wojciechowski, Discovering Diversity Corrections for Incompatible Web Services
A Parallel Scheme for Three-Dimensional Reconstruction in Large-Field Electron Tomography
DEER: A distributed routing scheme for achieving network energy efficiency
Identifying Semantic-Related Search Tasks in Query Log
Risk management for virtual machines consolidation in data centers
Low Execution Efficiency: When General Multi-core Processor Meets Wireless Communication Protocol
yaSpMV: Yet Another SpMV Framework on GPUs
Physically Based Parallel Ray Tracer for threMetropolis Light Transport Algorithm on the Tianhe-2 Su
Achieving High Throughput and Low Delay in Mobile Data Networks by Accurately Predicting Queue Lengt
ShiDianNao: Shifting Vision Processing Closer to the Sensor
A Secure Introspection Framework for Hardware Virtualization
Real-time Mixed Compression Scheme for Large-Scale Distributed Monitoring
A Hardware Assisted Recorder for User-Level Application
Achieving High Throughput and Low Delay by Accurately Regulating Link Queue Length over Mobile Data
Efficient and Flexible Index Access in MapReduce
Going Vertical in Memory Management: Handling Multiplicity by Multi-policy
Moby: A Mobile Benchmark Suite for Architectural Simulators
CMD: Classification-based Memory Deduplication through Page Access Characteristics
Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests
Functional Test Generation Guided by Steady-State Probabilities of Abstract Design
Partial-SET: Write Speedup of PCM Main Memory,
Wide Operational Range Power Delivery Design for both STV and NTV Computing
EATBit: Effective Automated Test for Binary Translation with High Code Coverage
Intelligent Frame Refresh for Energy-Aware Display Subsystems in Mobile Devices.
Dandelion: A Locally-High-Performance and Globally-High-Scalability Hierarchical Data Center Network
Pipelined Compaction for the LSM-tree
Post processing for dense stereo matching by iterative local plane fitting
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs,
A novel abstraction-guided simulation approach using posterior probabilities for verification
An Energy-Efficient Write Scheme for MLC PCM
Fuel Cell Generation in Geo-Distributed Cloud Services
Energy-Efficient Flow Scheduling and Routing with Hard Deadlines in Data Center Networks
a Distributed Routing Scheme for Achieving Network Energy Efficiency
A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations
Thermal-sustainable PowerBudgeting for Dynamic Threading
Dynamic and Adaptive Calling Context Encoding
A composite Approach to MitigateVoltage Droop Effects in 3D Power Delivery Network
A composite Approach to MitigateVoltage Droop Effects in 3D Power Delivery Network
Exclusive Memory Scheduling for Multimedia MPSoC
VBIW: Optimizing Indirect Branch in Dynamic Binary Translation
Luminance and Chrominance Parallelization of H.264/AVC Decoding on a Multi-core Processor
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Realizing Hardware Accelerated AVS Video Playback on the Godson Platform
A Low-Cost Memory Interface for High-Throughput Accelerators
Optimizing Memory Access with Fast Address Computation on a MIPS Architecture
Archipelago: A Floorplan Optimized for Concurrent Multiple Applications on Network-on-Chip
HERMES: A Fast Cross-ISA Binary Translator with Post-Optimization
MRP: Mix Real Cores and Pseudo Cores for FPGAbased Chip-multiprocessor Simulation
Dandelion: A Locally-High-Performance and Globally-High-ScalabilityHierarchical Data Center Network
Optimizing TCP Loss Recovery Performance overMobile Data Networks
AMTCP: An Adaptive Multi-path Transmission Control Protocol
Flyover: A Cost-Efficient and Scale-Out Data Center Network Architecture
Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Dema
SpongeDirectory: Flexible Sparse Directories Utilizing Multi-Level Memristors
RADAR: A Case for Retention-Aware DRAM Assembly and Repair in Future FGR DRAM Memory
ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Processing
Retraining based Timing Error Mitigation for Hardware Neural Networks
A Case of Precision-Tunable STT-RAM Memory Design for Approximate Neural Network
Persistent B+-Trees in Non-Volatile Main Memory
Energy-Efficient Flow Scheduling and Routing with Hard Deadlines in Data Center Networks
Polylogarithmic Competitive Algorithm for Energy Minimization in Optical WDM Networks
Synchronization Identification through On-the-fly Test
A Parallel Scheme for Three-Dimensional Reconstruction in Large-Field Electron Tomography
EPiK-a Workflow for Electron Tomography inKepler
A Collaborative Divide-and-Conquer K-Means Clustering Algorithm for Processing Large Data
Localization of concurrency bugs using shared memory access pairs
Real-time Mixed Compression Scheme for Large-Scale Distributed Monitoring
Polylogarithmic Competitive Algorithm for Energy Minimization in Optical WDM Networks
oint Power Optimization Through VM Placement and Flow Scheduling in Data Centers
Optimization of RAR password brute-force cracking based on OpenCL
Research on Histogram Generation Algorithm Optimization Based on OpenCL
Research of Viola-Jones Face Detection Algorithm Optimization Based on OpenCL
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ArchRanker: A Ranking Approach to Design Space Exploration
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EPiK-a Workflow for Electron Tomography inKepler
A Parallel Scheme for Three-Dimensional Reconstruction in Large-Field Electron Tomography
EPiK-a Workflow for Electron Tomography inKepler
Polylogarithmic Competitive Algorithm for Energy Minimization in Optical WDM Networks
oint Power Optimization Through VM Placement and Flow Scheduling in Data Centers
Optimization of RAR password brute-force cracking based on OpenCL
Research on Histogram Generation Algorithm Optimization Based on OpenCL
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Vlock: Lock virtualization mechanism for exploiting fine-grained parallelism in graph traversal algo
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Energy-Performance Modeling and Optimization of Parallel Computing in On-Chip Networks.
A Path-Adaptive Opto-Electronic Hybrid NoC for Chip Multi-Processor
An Efficient Parallel Mechanism for Highly-Debuggable Multicore Simulator
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