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A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer netw
  • 所属机构名称：复旦大学
  • 会议名称：IEEE International Solid-State Circuits Conference (ISSCC)
  • 时间：2013
  • 成果类型：会议
  • 相关项目：众核处理器容错性设计之研究
作者： Zheng Yu|Xueqiu Yu|Shile Cui|Jie Feng|Shikai Zhu|Jie Lin|Ming'e Jing|Xiaoyang Zeng|Zhiyi Yu|
同会议论文项目
众核处理器容错性设计之研究
期刊论文 7 会议论文 12
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