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A clock system for high speed and low power parallel link
  • 所属机构名称：中国科学院计算技术研究所
  • 会议名称：2007 International Symposium on Integrated Circuits, ISIC
  • 成果类型：会议
  • 会场：Singapore, Singapore
  • 相关项目：采用形式化引擎加速处理器仿真验证收敛的关键技术研究
作者： Wang, Zhiyuan|Zhang, Feng|Zhang, Ge|Yang, Yi|Gao, Zhuo|
同会议论文项目
采用形式化引擎加速处理器仿真验证收敛的关键技术研究
期刊论文 35 会议论文 22 专利 9
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