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A 65-nm 1-Gb NOR floating-gate flash memory with less than 50-ns access time
  • ISSN号：1001-6538
  • 期刊名称：Chinese Science Bulletin
  • 时间：2014.10
  • 页码：3935-3942
  • 分类：TP333[自动化与计算机技术—计算机系统结构;自动化与计算机技术—计算机科学与技术] TP312[自动化与计算机技术—计算机软件与理论;自动化与计算机技术—计算机科学与技术]
  • 作者机构：[1]Laboratory of Nano-fabrication and Novel Device Integration, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China, [2]Institute of Microelectronics, Tsinghua University,Beijing 100083, China, [3]Institute of Microelectronics, Peking University, Beijing 100871,China, [4]Semiconductor Manufacturing International Corporation,Shanghai 201203, China
  • 相关基金：Acknowledgements This work was supported in part by the Ministry of Science and Technology of China （2010CB934200, 2011CBA00600）, the National Natural Science Foundation of China （61176073）, the National Science and Technology Major Project of China （2009ZX02023-005） and the Director＇s Fund of Institute of Microelectronics, Chinese Academy of Science.
  • 相关项目：新型微电子器件集成的基础研究
作者： Yang, Yun|Qiu, Shenfeng|Wu, Hanming|Liu, Ming|
关键词： NOR闪存, 访问时间, GB, 浮栅, NS, 深亚微米工艺, 芯片电路, 速度问题, NOR floating-gate flash memory , 65-nm process , Giga bit size , Access time , Circuit design
中文摘要：

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be estimated.Based on that,the read path and key modules are optimized to enhance the chip access property and reliability.With the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.

英文摘要：

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR flash in the deep submicron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability. With the measurement results, the flash memory cell presents good endurance and retention properties, and the macro is operated with 1-las/byte program speed and less than 50-ns read time under 3.3 V supply.

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