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中文摘要：
片上互连网络已日益成为影响片上多处理器性能的重要因素之一．几乎所有的互连结构均是在二维网络的基础上演变发展而来的．首先分析了几种常见的内部结点度均为4的二维网络的静态特性，提出了一种新的二维片上网络互连路由结构和通信协议，基于全局均匀随机通信模型，通过改变网络规模和变换通信强度，分析了不同结构网络的动态特性，然后用链接数表示通信成本，提出了一种新的网络互连综合性能评估指标网络单位成本延迟负载能力，最后对二维网络片上互连的综合性能进行了对比分析，指出了其各自适用的场合．
英文摘要：
The interconnection networks-on-chip becomes an performance of chip-multiprocessor. Almost all interconnection networks. After analyzing the static networks characteristics of important factor structures evolve some popular 2-D affecting the from the 2-D interconnection networ networ port ra the net ks-on-chip whose inner-nodes degree is 4, the authors propose a kind of interconneetion ks-on-chip router and the communication protocol. The router uses buffers just on the outside ther than on both the inside and the outside port to reduce the power and increase the speed in works transmission. Based on the analysis of the dynamic networks characteristics of those different structures by changing the scales and the loads, load per cost-delay product, a new evaluation to the all-sided performance of interconnection networks-on-chip, is proposed using the link to indicate the cost. Finally, the all-sided performance of those different 2-D intereonnection nelworks on-chip structures iS analyzed and the suitable cases for e~tch structure is indicated. The cxperinlentM resuhs show th~tt in the case of small-scale under low load the multi-ring networks do well and in the case of larger-scale under larger load mesh grids work better. The wrap around structures is the first choice as long as it could be. However, in the case of large-scale, it is difficult to get good performance by just adopting any one of those structures directly.
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