通过共用小卫星与小运载的电子系统,能够降低卫星发射成本、实现卫星与运载的快速集成及测试、减少卫星的发射与入轨时间,从而达到快速响应自然灾害等突发事件的目的。传统航天器电子系统难以兼顾运载段任务的高实时性和在轨段任务的高可靠性要求,因此本文将多核处理器技术、可重构技术和航天器电子系统设计相结合,提出了基于可重构技术的小卫星/小运载多核计算机设计方案。该设计方案分为运载和在轨两种工作模式,通过现场可编程门阵列(FPGA)的快速重构来实现计算机两种工作模式的快速切换。其中运载模式将FPGA配置成并行构架的三核处理器,通过3个处理器并行计算来提升计算机的处理能力;在轨模式将FPGA配置成冗余构架的三核处理器,通过3个处理器互为冗余备份来提升计算机的长期可靠性。经过基于Markov过程理论的系统可靠性分析,表明系统在轨段的长期可靠性得到显著提升。同时经过地面半物理仿真系统仿真测试,运载段的控制周期可以达到10ms,满足运载段任务的实时性要求。
One of the most important directions of modern small satellite technology development is to enable a small satellite to respond rapidly to emergencies with relatively low launching cost and design cost. Using integrated electronic systems which are shared by both the rocket and the satellite can reduce the cost and time. The traditional electronic system of a space vehicle cannot meet the needs of the mission of both the rocket and the satellite. Hence a method is advanced which integrates multi-processor technology,reconfiguration technology and the electronic system design of space vehicles. The method is aimed at designing an electronic system which can fulfill the needs of both the rocket and the satellite,whilst it should be no heavier,no bigger,no more expensive and even cheaper than the traditional system. According to the mission needs of the rocket and satellite,two types of three-core processors are designed in a reconfigurable field programmable gate array (FPGA) whose reconfiguration is based on the mission period. This FPGA can make the electronic system work efficiently in both the rocket period and the satellite period. Ground real-time simulation system is established to verify the performance and reliability of the reconfigurable multi-processor on-board computer.