位置:成果数据库 > 期刊 > 期刊详情页
“银河飞腾”高性能数字信号处理器研究进展
  • ISSN号:1000-1239
  • 期刊名称:《计算机研究与发展》
  • 时间:0
  • 分类:TP302[自动化与计算机技术—计算机系统结构;自动化与计算机技术—计算机科学与技术]
  • 作者机构:[1]国防科学技术大学计算机学院,长沙410073
  • 相关基金:国家“八六三”高技术研究发展计划基金项目(2004AA1Z1040);国家自然科学基金项目(60473079) Digital signal processor (DSP) is a special kind of embedded microprocesmr with an emphasis on arithmetic computation. It has gained great interests from both the industry and the academic. This paper introduces the successful commercial DSP architectures and the latest research in academic. YHFT-DSP/700 is a high performance floating point DSP developed by NUDT's DSP Design Group leaded by Prof. Chen Shuming. YHFT-DSP/700 has 8 execulion units, including 4 ALUs, 2 multipliers and 2 load/store units. Its VLIW architecture can issue 8 instructions per cycle. When running at the frequency of 238MHz, its peak performance is 1, 428MFL0PS and 1,904MIPS. YHFT-DSP/700 uses a packed variable length instruction packet technique, which can reduce the program memory usage. The support of 8 bit and 16-bit SIMD instructions can double the chip's performance for some multimedia algorithms. YHFT-DSP/700 has a two level memory hierarchy. YHFT-DSP/700 is fabricated in 0.18 micron CM0S process. The register file and the barrel shifter are designed in full custom. To help the programmers, a VLIW compiler is designed. 0n this basis, we implement an integrated development environment, and M0SI, a new simultaneous multi-threading DSP architecture, is also presented. It can improve the system throughput by 40 % . This work is supported by the National High Technology Research and Development Program of China (2004AAIZ1040) and the National Natural Science Foundation of China (60473079).
中文摘要:

YHFT—DSP/700是2004年研制成功的“银河飞腾”系列超长指令字结构高性能浮点DSP,其主频达238MHz,峰值性能为每秒14亿次浮点运算和19亿条指令,介绍了YHFT—DSP/700的体系结构、设计方法和编译器等关键技术;介绍了同时多线程YHFT—DSP/SMT的体系结构,它可以将DSP的性能提高40%;分析了国际主流高性能DSP的体系结构和发展趋势.

英文摘要:

YHFT-DSP/700 is a high performance floating-point VLIW DSP developed in 2004. Its frequency is 238MHz and its peak performance is 1,428MFLOPS and 1,904MlPS. The architecture, design methodology and compiler techniques of YHFT-DSP/700 are presented. The latest simultaneous multi-threading DSP architecture called YHFT-DSP/SMT is proposed, which improves the system throughput by 40 %. The architecture and development trends of the mainstream high performance DSPs are analyzed as well.

同期刊论文项目
同项目期刊论文
期刊信息
  • 《计算机研究与发展》
  • 中国科技核心期刊
  • 主管单位:中国科学院
  • 主办单位:中国科学院计算技术研究所
  • 主编:徐志伟
  • 地址:北京市科学院南路6号中科院计算所
  • 邮编:100190
  • 邮箱:crad@ict.ac.cn
  • 电话:010-62620696 62600350
  • 国际标准刊号:ISSN:1000-1239
  • 国内统一刊号:ISSN:11-1777/TP
  • 邮发代号:2-654
  • 获奖情况:
  • 2001-2007百种中国杰出学术期刊,2008中国精品科...,中国期刊方阵“双效”期刊
  • 国内外数据库收录:
  • 俄罗斯文摘杂志,荷兰文摘与引文数据库,美国工程索引,日本日本科学技术振兴机构数据库,中国中国科技核心期刊,中国北大核心期刊(2004版),中国北大核心期刊(2008版),中国北大核心期刊(2011版),中国北大核心期刊(2014版),中国北大核心期刊(2000版)
  • 被引量:40349