中文摘要：

Grostl是继承MD迭代结构和沿用AES压缩函数的SHA．3候选算法。目前的研究只针对Grostl算法的一种或两种参数版本进行实现，并没有针对Grcstl四种参数版本的设计，缺少灵活性。在分析Gr#stl算法的基础上，采用可重构的设计思想，在FPGA上实现了Grcstl四种参数版本。实验结果表明，在XilinxVirtex一5FPGA平台上，四参数可重构方案的面积为4279slices，时钟频率为223．32MHz，与已有的实现方法相比，具有面积小、时钟频率高及灵活性等优点。

英文摘要：

Grostl algorithm is one of SHA-3 finalist which is mainly composed of Message Digest （MD） iteration and AES compression function. Previous research work has been done on hardware implementation of Grostl algorithm, but the disadvantage of their implementation lies on only focusing on one or two parameters version of Grcstl and less flexibility. Base on the analysis of Grostl algorithm, this paper proposes a new reconfigurable architecture which can support four different parameters of Grostl algorithms. The proposed design ports to Xilinx Virtex-5 FPGA platform and achieved 223.32 MHz clock frequency using 4 279 slices. The experimental results show that the proposed design has smaller size, higher clock frequency and more flexibility supporting compared with the exist ng work when ports to FPGA platform.