中文摘要：

为了提高SRAM的成品率并降低其功耗，提出一种优化的SRAM．通过增加的冗余逻辑及电熔丝盒来代替SRAM中的错误单元，以提高其成品率；通过引入电源开启或关闭状态及隔离逻辑降低其功耗．利用二项分布计算最佳冗余逻辑，引入成品率边界因子判定冗余逻辑的经济性．将优化的SRAM64K×32应用到SoC中，并对SRAM64K×32的测试方法进行了讨论．该SoC经90nmCMOS工艺成功流片，芯片面积为5．6mm×5．6mm，功耗为1997mw．测试结果表明：优化的SRAM64K×32在每个晶圆上的成品率提高了9．267％，功耗降低了17．301％．

英文摘要：

In order to improve the yield of SRAM and reduce its power consumption, an optimized SRAM is presented. Redundancy logic and E-fuse box are added to replace the faulty units of SRAM for higher yield; power on/off states and isolation logic are introduced to reduce power consumption. By means of binomial distribution the optimum redundancy logic is calculated and the boundary factor of yield is introduced to determine whether the redundancy logic is worthy. The optimized SRAM64K×32 is used in SoC and the testing method of the SRAM64K×32 is discussed. The SoC design has been successfully implemented in a chartered 90 nm CMOS process. The SoC chip occupies 5.6mm× 5.6mm of die area and consumes 1997 mW. The testing results indicate that the yield of SRAM64K×32s per wafer is improved by 9. 267% and the power saving is 17. 301%.