中文摘要：

对多元ZnO压敏陶瓷电阻片进行了多达14000次的大电流冲击老化试验,通过显微结构、电气性能及介电特性的测量对其缺陷结构进行了表征,并研究了缺陷结构与大电流冲击老化之间的关系.试验表明多次大电流冲击老化导致试样的电气性能明显下降,发现ZnO压敏陶瓷的几何效应不仅受控于晶粒还与晶界密切相关.另外,通过介电谱分析观察到ZnO压敏陶瓷存在四种缺陷弛豫过程,低温-60℃下的两个缺陷弛豫峰激活能约为0.24 eV和0.35 eV,认为它们分别对应着本征的锌填隙缺陷L（Zni¨）和氧空位缺陷L（Vo＇）并且不受冲击老化的影响.高温80℃以上两个松弛峰的活化能约为0.71 eV和0.84 eV,认为它们分别对应着非本征的晶间相电子陷阱L（ingr）和晶界处界面态陷阱L（gb）.发现大电流冲击后,仅界面态陷阱激活能从0.84 eV降低到0.76 eV,认为界面态陷阱主要控制着ZnO压敏陶瓷的电气性能和稳定性.

英文摘要：

The electrical and dielectric properties and the microstructures of a polynary ZnO-based varistor ceramics with 14000 times impulse current aging test are measured.The relationship between defect structure and impulse current aging is mainly investigated. It is found that the electrical properties decrease rapidly with impulse aging and the dimensional effect of ZnO varistor ceramics is dominated not only by grain but also by grain boundary.Additionally,four defect relaxations are found at different temperatures by using dielectric spectra.Two defect relaxations appearing below—60℃with activation energies about 0.24 eV and 0.35 eV are identified to be intrinsic defects originating from interstitial Zn L（Zn_i） and vacancy oxygen L（V_o）,which are not affected by impulse current aging.Other two relaxations appearing above 80℃are suggested to be extrinsic defects originating from trap levels L（ingr） at intergranular phase and trap levels L（gb） at grain-boundary interfaces,respectively.Only L（gb） decreases from 0.84 eV to 0.76 eV due to impulse current aging while other trap levels keep unchanged.It is further proposed that L（gb） is responsible mainly for the electrical property and stability of ZnO ceramics.