中文摘要：

并行加权比特翻转算法（PWBF）可以获得好的译码性能，但其比特选择机制计算较为复杂，不利于硬件实现．通过对PWBF算法比特选择机制的改进，提出一种低复杂度的低密度奇偶校验码（LDPC）译码算法．具体来讲，每次迭代过程中，当完成所有比特的品质因素更新后，挑选品质因素最大的若干比特进行翻转译码．另外，笔者对算法关键模块的硬件实现进行分析，分别给出了计算优化的电路结构设计．与PWBF算法相比，笔者提出的算法和优化技术大大降低了LDPC译码器的复杂度．

英文摘要：

Parallel Weighted Bit Flipping（PWBF） can achieve a good decoding performance. However, it is hard for the hardware design and implementation because of the high complexity of its bit-chosen mechanism. By improving the bit-chosen mechanism in PWBF, a low-complexity decoding algorithm is proposed in this paper. Especially, in each iteration step of decoding, after the metric value of every bit is updated, several bits with the largest metric values are flipped. Furthermore, the optimized circuits with low complexity are provided for the critical modules of the proposed algorithm. Compared with the PWBF algorithm, the complexity of LDPC decoders is greatly decreased by use of the proposed algorithm and the optimized circuits.