中文摘要：

片上多处理器中不同核的缺失地址序列之间通常存在一定的空间和时间相关性,为了充分利用该性质,本文提出时空结合的数据预取.该机制首先寻找核内缺失地址序列的相关性,在核内探索不到的情况下再寻找核间的相关性,因此可利用其它核的访存行为来预测本核可能即将发生的访存行为.实验结果表明,本文提出的数据预取机制可使测试程序的平均性能提高12.6%,与扩展应用在多核上的C/DC策略相比较,性能提高了3.8%.

英文摘要：

The miss addresses of multiple cores often have some spatial correlation and temporal correlation in chip multiprocessors.In order to make full use of the properties,this paper proposes Spatio-Temporal data prefetching which exploits inter-core correlation when it don′t find intra-core correlation in a core,so it can predict future memory access through other cores.The experimental results indicate that the proposed mechanism can get an average of 12.6% speedup when compared with no prefetching.Meanwhile,compared with C/DC,it improves performance by 3.8%.