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多线程非阻塞指令Cache设计
  • ISSN号：1000-7180
  • 期刊名称：《微电子学与计算机》
  • 时间：0
  • 分类：TP338.6[自动化与计算机技术—计算机系统结构;自动化与计算机技术—计算机科学与技术]
  • 作者机构：[1]华中科技大学图像识别与人工智能研究所,湖北武汉430074, [2]华中科技大学多谱信息处理技术国家级重点实验室,湖北武汉430074
  • 相关基金：国家自然科学基金（60736010）
作者： 胡孔阳[1,2], 陈鹏[1,2], 桑红石[1,2]
关键词： 多线程, 非阻塞, CACHE, SystemVerilog仿真模型, multithreading, non-blocking, cache, SystemVerilog, simulation mode
中文摘要：

非阻塞Cache是指Cache在等待预取数据返回时，还能继续提供指令和数据．首先分析了多线程非阻塞Cache的处理器需求，然后提出其时序要求和一种实现方案．利用SystemVerilog对该方案进行RTL级建模和性能评估．仿真结果表明，该方案可以很好地应用于多线程、乱序执行处理器的指令引擎设计之中．

英文摘要：

Non-blocking instruction Cache is one Cache that can continue to provide instruction and data, when waiting for the prefetch data. In this paper, first analyze the processors＇ demand for multithreading non-blocking cache, then put forward the timing request and the functional structure. SystemVerilog is employed to build up the simulation model of the proposed architecture and the performace evaluation. Evaluation results show that the architecture can be applied to the design of fetch engine in multithreading or out of order execution processors.

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期刊信息
  • 《微电子学与计算机》
  • 中国科技核心期刊
  • 主管单位:中国航天科技集团公司
  • 主办单位:中国航天科技集团公司第九研究院第七七一研究所
  • 主编：李新龙
  • 地址：西安市雁塔区太白南路198号
  • 邮编：710065
  • 邮箱：mc771@163.com
  • 电话：029-82262687
  • 国际标准刊号：ISSN：1000-7180
  • 国内统一刊号：ISSN：61-1123/TN
  • 邮发代号:52-16
  • 获奖情况:
  • 航天优秀期刊,陕西省优秀期刊一等奖
  • 国内外数据库收录:
  • 荷兰文摘与引文数据库,日本日本科学技术振兴机构数据库,中国中国科技核心期刊,中国北大核心期刊（2004版）,中国北大核心期刊（2008版）,中国北大核心期刊（2011版）,中国北大核心期刊（2014版）,中国北大核心期刊（2000版）
  • 被引量:17909