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中文摘要：
为了降低指令分派造成的运行开销以提高解释器的性能,提出了一种采用软硬件协同设计的解释器指令分派方法。其核心思想是在软件层面通过对指令分派表进行优化以消除了代价较高的地址常量加载操作,在硬件层面通过扩展处理器的访存指令进一步实现基于硬件支持的访存加速。软硬件协同设计可以最大限度地降低由指令分派引入的运行时开销,从而提升解释执行的效率。试验结果表明,该方法能够显著提升解释器的性能。对于SPECjvm98和Da Capo测试集,解释器总体性能提升了11.5%,且单项性能的最大提升幅度高达15.4%。该方法通用性强,实现代价低,适用于现代主流处理器平台上高性能解释器的设计和优化。
英文摘要：
To reduce the overhead caused by instruction dispatch to improve the performance of interpreters,an instruction dispatch approach based on hardware and software co-design is proposed. Its main idea is to eliminate the expensive operation of constant address loading by optimizing the instruction dispatch table in the aspect of sofware,and to acceleratethe speed of memory access under the support of hardware by enhancing the processor＇s instruction set in the aspect of hardware. The hardware-software co-design can minimize the runtime overhead of instruction dispatch,thus improving the performance of interpreters. The experimental results showed that the proposed approach significantly improved the performance of interpreters. For benchmarks of SPECjvm98 and Da Capo,the overall performance of interpreters was improved by 11. 5%,and the highest performance boost was up to 15. 4%.The approach is highly versatile,easy to implement and can be applied to the design and implementation of high performance interpreters on mainstream processors.
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