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中文摘要：
工艺波动下3D IC的成品率受绑定策略的影响较大.为了减少不当绑定造成的成品率损失,提出一种基于关键通路时延的3D IC绑定优化方法.通过绑定前时延测量得到待绑定芯片各层的时序特性,利用不同层上的通路进行时延互补,使用＂好＂的芯片挽救＂坏＂的芯片;把最大成品率问题抽象成二分图的最大匹配问题,提出了分级和啮合两种绑定优化算法,采用增广路经算法进行求解.实验结果表明,相对于不考虑工艺波动的随机绑定方法,采用文中方法有效地提高了3D IC的成品率.
英文摘要：
Under impacting of process variation,the yield of the 3D IC mostly depends on the bonding strategies.In order to reduce the yield loss due to unmerited bonding orders,this paper proposes a bonding optimization method based on critical path delay to improve the yield in 3D chips bonding process.Path delay measurement is employed to obtain the timing characteristics of the pre-bond chips;and the chip with long paths is bonded to the one with short paths in different layers,which means use good one to save bad one.Two matching algorithms called grading and toothing are presented by formalizing the max yield problem with bipartite graph maximum matching model.Experimental results show that the proposed bonding method achieved much higher yield compared to random bonding.
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