针对密码算法用户对于多种对称密钥算法高效可配的使用需求,设计一种新的对称密钥算法硬件架构。根据各密钥算法的特点,分析其运算逻辑并进行拆分,使用基础运算单元可重构方法将各算法实现在同一运算核心模块上,在保证电路时序的情况下,节约电路的整体面积,提高电路的单位面积吞吐率。该架构具有较好的扩展性,便于新对称密钥算法的进一步重构实现。仿真结果表明,该架构在实现同类算法时,电路面积和单位面积吞吐率均优于状态阵列重构、s盒查找表优化等架构,在实现多种算法时,其面积增加也较少。
To meet the users' needs for a variety of algorithms, this paper presents a symmetric key algorithms hardware architecture. It analyzes every algorithms and makes a logic separation, based on the characteristics of each algorithm. It efficiently implements various algorithms in the same operation module by using basic arithmetic unit reconfigurable method. The architecture is easily to extend with a new symmetric key algorithm. Simulation results show that the proposed architecture has a better throughput and uses smaller area than the existing design (cell array reconfigurable architecture, LUT optimized architecture, e. g. ) while implementing the same kind of algorithm. To implement more al~orithm~ it h~ ,, ,