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中文摘要：
为了削减芯片在测试过程中由于测试向量移入/移出所导致的静态功耗和动态功耗,提出一种电源屏蔽实现方法.在后端设计布局阶段,首先以时钟门控单元为参考点将触发器聚类摆放,以实现时序逻辑与组合逻辑在物理上的隔离;然后引入屏蔽单元对电源网络进行修改,最终解决扫描触发器与组合逻辑异构供电的难题.针对龙芯3号浮点乘积模块的实验结果表明,采用该方法可以节省45%的测试功耗,面积稍有增加,而对性能和测试覆盖率几乎没有影响,并且可以容易地嵌入目前的主流设计方法中.
英文摘要：
To reduce dynamic power and static power in the shift process of test procedure,a novel power gating implementation scheme is proposed.During placement phase of backend design,the registers are placed together based on the location of clock gating cells so as to physically isolate with the combinational logic.After that,power/ground network is tailored under the requirements of power gating cells.At last,the difficulties of providing separate power supply for registers and combinational logic circuits are resolved.The evaluation results on Godson-3 floating-point fused multiply-add block show that around 45% of the test power can be reduced with some penalties of area increase and no performance and test coverage degradation occurs.Moreover,it can be easily integrated into the mainstream design method.
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