中文摘要：

在FPGA芯片实现的DDS信号发生器已有一定的应用范围。为获得较宽的频率输出范围，一般需要存储相当数量的波形离散值，占用大量的芯片逻辑资源；这篇文章研究在存储较少量的波形离散值的情况下，通过对系统时钟进行分频，减小输出频率最小值，同时提高在低频处的频率分辨率，通过设定频率控制字为存储离散值个数的约数，保证输出波形重构良好、频率失真度低，节约芯片资源；该设计方案可输出多种波形，其中方波占空比亦可调节，将幅度调节设计在模拟运放电路中，可对幅度进行连续调节；整体设计软件化、模块化，易于调整和扩展；经验证，本设计方案可行，达到预期效果，有一定的工程指导意义和实用价值。

英文摘要：

DDS signal generator in the FPGA chip has a certain range of applications. To obtain a wide range of output frequency, the generator need to store a considerable number of discrete values of waveform, which will take up a large number of chip logic resources. We make research on that with a lower amount of discrete values stored, the generator can reduce the minimum output ：frequency and improve the frequency resolution in the low frequency by dividing system clock. We set the frequency control word to ensure the quality of waveform re- construction and the low degree of frequency distortion, saving the chip resources. The generator we designed can output a variety of wave- forms, and the duty ratio of square wave can be regulated. The amplitude regulation is designed in analog amplifier circuit, so the amplitude can be regulated continuously. The overall design of hardware and software is modular and easy to adjust and extend. It is proved that the de- sign is feasible and achieve the expectation, which means that the design has a certain engineering significance and practical value.