中文摘要：

众核芯片系统存在吞吐量低、加速比不能与其片内处理核数的增长成线性比例等问题，无法发挥出相应的计算能力，目前的众核微体系结构并不匹配MapReduce运行时．针对上述问题，为实现高性能众核芯片系统巨大计算和处理能力目标，文中分析了众核MapReduce的执行模型，基于DOT模型构建了众核存储体系，对其中的片上网络、通信模式、访存流程及基于此的MapReduce存储模式进行了设计．实验数据表明，和Tile结构相比，基于该三维存储体系的众核系统的吞吐量能提高1．2倍，加速比和片内处理核数接近线性关系．

英文摘要：

The current many-core micro architecture does not match the MapReduce run-time, so there exist problems such as the low throughput, and the fact that speedup cannot be proportional to growth of cores, which makes many-core chip system unable to get deserving computing capability. This paper aims to solve these problems and achieve huge computing capability in the high performance many-core chip system. Firstly, the executing module for many-core MapReduce was analyzed. Then, a new three-dimensional （3D） memory architecture was proposed based on DOT module which included the designs of network-on-chip, communication module, the procedure of accessing memory and access module for MapReduce. Experimental results have shown that compared with tile structure of many-core system, the throughput of 3D storage system-based many-core system can increase more than 1.2 times, the speedup is proportional to the number of cores.