欢迎您！东篱公司
退出
-
申报数据库
-
立项数据库
-
成果数据库
-
项目获奖数据库
中文摘要：
介绍深亚微米工艺下超大规模集成电路的互连线寄生电容提取问题，实现了基于神经网络的互连线寄生电容模型的建模与仿真，重点讨论了在建模过程中神经网络模型结构的选择，数据样本的处理，神经网络模型的训练，神经网络模型的测试等问题．实验结果表明，良好训练后的神经网络模型不仅在仿真中能够快速、准确地输出互连线寄生电容值，而且具备良好的泛化能力，从而满足了集成电路设计特别是布局布线优化设计的要求．
英文摘要：
A new approach for parasitic capacitance extraction of VLSI interconnects was presented by making use of neural networks. （very large scale integration） Neural network modeling and simulation were developed for parasitic capacitance extraction. Some important steps in neural networks, preprocess dates, train and test the neural networks models. Simulation results demonstrated that well-trained neural network models had strong capabilities of efficiently generalizing and producing the accurate responses, which met the needs of optimization design in VLSI.
同期刊论文项目
同项目期刊论文
期刊信息
位置：