中文摘要：

为了在时序逻辑综合中使电路面积和关键路径延迟同时得到快速优化，提出一种改进的基于假设后验证的时序优化算法。在位并行随机模拟提取候选属性不变量之前，利用寄存器共享来降低初始候选不变量数目，以减少SAT程序的频繁调用；然后利用推测化简模型和改进的数学归纳法将基本条件和归纳步骤合并处理，有效地降低了电路规模和关键路径延迟，同时提高了算法运行速度．实验数据表明，文中算法使寄存器和节点规模平均下降41％和48％，关键路径延迟减小30％；与同类方法相比，该算法运行时间平均下降17％．

英文摘要：

To optimize the circuit area and critical path delay simultaneously and fast in sequential synthesis, this paper presents an improved sequential logic optimization algorithm based on an ＂assume-then-prove＂ principle. Prior to applying bit-wise parallel simulation to derive initial candidate invariants, the algorithm makes use of registers sharing to reduce the number of the initial candidate invariants, with which the number of times in calling the SAT procedure can be decreased. Then, it merges the processes of base case and induction steps to improve the induction utilizing speculative reduction model. Therefore it can effectively reduce both the area and critical path delay of the implementation circuits, and improve the computational speed. Experiment results show that the presented algorithm achieves an average reduction in number of the registers and the number of the logic nodes by 41% and 48% respectively, and the critical path delay can be reduced by 30% on average. In comparison with similar method, the average runtime of the new algorithm decreased ：7%.