中文摘要：

在L波段数字航空通信系统（L—DACS1）中，不同类型的数据采用不同速率传输，为了降低信道的噪声和畸变与多普勒频移的影响，采用具有良好差错控制能力的多速率卷积编码进行信道纠错。通过利用VerilogHDL硬件描述语言完成其FPGA实现与验证，测试结果表明多速率卷积编码器可以实时地调整码率，高效稳定地进行差错控制，满足L—DACS1高速传输仍保持稳定的要求，并且用于实际项目中。

英文摘要：

In the L-DACS1, different types of data transmits at different rates. In order to reduce the noise and distortion and the influence of Doppler shift, multi-rate convolution code with the good ability of error control is used for channel error correction. Then, Verilog HDL, a hardware descripton language, is adopted for FPGA implementation and verification of multi-rate convolution coder. Test results show that the multi-rate convolution coder can adjust coding rate instantaneously with stable and efficient error control, and meet the requirements of the stability under the condition of high speed tansmission in L-DACS1, which is used in actual projects.