中文摘要：

当前纳米互补金属氧化物半导体（complementarymetaloxidesemiconductor，CMOS）集成电路设计中，利用电源门控（powergating，PG）技术来降低静态功耗已成为一种趋势。随着集成电路工艺尺寸的不断缩小，负偏置温度不稳定性（negativebiastemperatureinstability，NBTI）带来的电路老化问题越来越严重。当Header型PG电路处于正常工作模式时，休眠管（sleeptransistor，ST）会受到NBTI老化效应的影响，导致PG电路的性能损失加重。文章通过对PG电路的NBTI老化特性分析，提出了考虑NBTI的PG电路性能损失模型；利用PG电路的NBTI老化特性将ST进行分组，并通过间断接通ST，等效于动态调节ST的尺寸或导通电阻，来减小由ST老化引起的PG电路性能损失。结果表明，动态ST尺寸方法与传统ST尺寸方法相比，可以使PG电路的使用寿命提高30％左右，并且提出的模型与HSPICE仿真结果所得到的趋势相吻合。

英文摘要：

For nano-meter scale complementary metal oxide semiconductor （CMOS） integrated circuit design, using the power gating（PG） technology to reduce static power dissipation has become a main- stream trend. With the shrinking Of integrated circuit technology size, the circuit aging effect induced by negative bias temperature instability（NBTI） is getting worse. When a Header-type PG circuit is in operative mode, the PMOS sleep transistor（ST） is negatively biased and will suffer serious NBTI effect, resulting in circuit performance loss. Through the analysis of the NBTI induced PG circuit ag- ing, a model to predict the NBTI-aware performance loss of PG circuit is proposed. By grouping the STs, a method in which the ST groups are opened discontinuously to dynamically adjust the ST size or its;on-resistance is proposed. The simulation results show that compared to the ST static over-sizing method, the proposed method can increase the lifetime of the PG circuit by about 30% on average. And the simulation results by HSPICE are basically consistent with the results predicted by the pro- posed model.