中文摘要：

提出了在FPGA（现场可编程门阵列）上实现1024点基4-FFT（快速傅里叶变换）算法的设计方案。方案对FFT算法的核心单元即蝶形运算单元的结构进行了分析和优化，用一个复乘器通过时序控制实现了和3个复乘器同样的效率，而且对整个算法的流程采用了流水线式的工作控制方式，不仅节省了FFT在FPGA上实现时占用的硬件资源，并且极大地提高了算法的运算效率。最后给出了仿真实验结果，并同MATLAB的FFT运算结果进行了对比。结果显示，在100MHz时钟条件下，本方案完成1024点的基4．FFT运算仅需51．28μs，完全满足高速FFT运算的实时性要求。

英文摘要：

The paper proposes the implement scheme of the 1024 points radix4 DIT FFF algorithm on FPGA. The butterfly unit , which is the core of the algorithm, is analysed and optimized . Due to timing controlling , the developed butterfly unit uses only one complex multiplier and has the same efficiency to the three multiplier structure. The processor is working in pipeline, which made the implement of the FFT algorithm on FPGA is both area and speed efficient. The simulation result is presented in the last section and compared with the FFT result using MATLAB. It shows that the total simulation time of the 1024 points FFT is 51.28 μs when operated at 100 MHz clock, which well meets the demands of high speed FFT alogrithm.