中文摘要：

测试激励压缩方案能减少内建自测试（BIST）电路的存储硬件开销,适合超大规模集成电路的测试.将聚类压缩与循环移位压缩和输入精简压缩巧妙结合,提出一种针对BIST的测试激励聚类压缩方法.首先将难测向量进行x方向输入精简;然后以贪心选择的方法进行y方向聚类压缩,即将测试向量集划分成几个子集,每个子集只存储一个种子向量;最后将聚类后的种子向量集进行z方向移位压缩,将最终的种子向量存储到BIST电路中.测试时,解压电路通过对种子向量进行解压得到全部的难测向量.理论分析和实验结果表明,通过增加相对很少的硬件开销构建聚类移位输入精简解压电路能够产生较高的测试数据压缩率,减少测试向量存储单元,且能以芯片频率进行测试,其中对电路s38584的压缩率高达99.87％.

英文摘要：

Test pattern compression methods can reduce the memory requirements of build-in self-test （BIST）.They are more fitting for VLSI test,and hence a clustering compression method and a novel architecture are presented for deterministic BIST test pattern compression.Clustering compression is a method which uses a greedy algorithm to divide the test pattern into several clusters,and use only one special pattern to represent each cluster.The presented architecture relies on a three-dimensional compression scheme which combines input reduction,clustering compression and rotation-based compression.Firstly,it compresses the test set of random pattern resistant faults （RPRF） by input reduction in x direction.Secondly,it compresses the input reduction set by clustering compression in y direction.Finally,it compresses the clustered set by rotation-based compression in z direction.The rotation-based compressed set are then stored in the ROM of BIST circuit.Decompress the data set in the ROM will get all the RPRF when testing.Theoretical analysis and experimental results showed that the presented scheme can enormously reduce the hardware overhead of BIST circuit.Furthermore,the circuit under test can be testing at-speed.The compression rate of benchmark s38584 can even obtain 99.87％ when applying the presented scheme.