中文摘要：

随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET（metal-oxide-semiconductor field effect transistor）的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS（complementary metal oxide semiconductor）逻辑电路的影响。仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm。研究结果表明：边缘直接隧穿电流是小尺寸MOS器件栅直接隧穿电流的重要组成成分;漏端偏置和衬底偏置通过改变表面势影响栅电流密度;CMOS逻辑电路中MOS器件有4种工作状态,即线性区、饱和区、亚阈区和截止区;CMOS逻辑电路中MOS器件的栅泄漏电流与其工作状态有关。仿真结果与理论分析结果较符合,这些理论和仿真结果有助于以后的集成电路设计。

英文摘要：

With the scaling of MOS （metal-oxide-semiconductor） devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents, considering that, the direct tunneling current （DT） in MOSFET （metal-oxide-semiconductor field effect transistor） was studied based on reliability theory and simulation. Simultaneously, the static gate leakage current of two-input nor gate was studied and the impact of direct tunneling gate leakage current on CMOS （complementary metal oxide semiconductor） logic circuits was revealed. HSPICE software was used as the simulation tool. MOS model parameter is BSIM4 and LEVEL 54. The thickness of the gate oxide is 1.4 nm. The results show that the edge direct tunneling is an important component of gate tunneling in a scaled MOS device. Drain bias and substrate bias can affect the gate current density by changing the surface potential. There are four common working states of MOS device in CMOS logic circuit, i.e. the linear region, saturation region, sub-threshold region and cut-off region. The gate leakage current of MOSFET in CMOS logic circuit is related to its working status. The simulation results agree well with theoretical analysis results, and the theory and simulation will contribute to integrated circuit design.