为了满足日益提高的通信安全需求,缩短实时加解密处理的时间,提出了一种利用CPRS(混沌伪随机序列)加密算法,实现基于FPGA(现场可编程门阵列)的加解密芯片的算法设计。利用FPGA的并行流水线达到了DSP不能达到的处理速率和实时效果。该系统采用RAM分布式存储方式代替寄存器和case选择语句,减少资源利用率的同时获得最高100Mbps全双工加解密速率,满足当今对加密芯片越来越高的速率要求。该加密芯片可用于对语音、图像以及视频等的加密。
To satisfy the increasing requests of secure communication and reduce the processing time of real-time encryption/ decryption,a design method of FPGA(field-programmable gate array) chip based on CPRS(chaotic pseudo random sequence) algorithm is presented.The parallel pipeline of FPGA can reach an excellent real-time rate,while the DSP cannot.And a RAM(distributed storage mode) is used to replace the register and the case statement.The optimized full-duplex rate of encryption/decryption can achieve 100Mbps which satisfies the requests of real time encryption.The CPRS chip can be widely used in real-time transmission for voice,image and video encryption.