中文摘要：

随着多种视频编解码标准和视频算法的提出,视频处理器高效性和灵活性显得更为重要.针对视频阵列处理器中数据加载速率与阵列处理单元处理不匹配的问题,通过对视频编解码标准算法的分析,深度挖掘数据访存冗余和传输的特点,在可编程可重构体系结构下,设计了支持灌入和Cache两种工作模式的数据加载电路,并进行了功能仿真和FPGA验证.结果表明,该电路能够满足1 080P视频处理对数据加载的要求,采用Desgin Compiler在SMIC 0.13μm CMOS工艺标准单元库下综合,频率可达197 MHz.

英文摘要：

With a variety of video codec standards and video algorithms proposed,the efficiency and flexibility of video processor become more important.To solve the mismatch of data loading rate and array processing unit,analyzing the video codec standard algorithm,deep mining characteristics of data memory access redundancy and transmission,this paper designs a data loading circuit supporting pump and Cache operating modes in the programmable reconfigurable architecture,and also completes the functional simulation and FPGA verification to the circuit.The result show that this design can meet the data loading requirements of 1 080P video processing for data loading,and its integrated frequency up to 197 MHz,using Desgin Compiler in SMIC 0.13 μm CMOS process standard cell library.