中文摘要：

为了解决上下文自适应二进制算术编码器（CABAC，Context-based Adaptive Binary Arithmetic Coder）硬件实现吞吐率难以提高的问题，提出了基于数据流动态特性的电路优化方法．通过建立算法的数据流模型，提取出限制硬件实现性能的数据流反馈环路．针对上下文环路，采用3条迭代周期不同的子环路更新具有不同依赖周期的上下文变量，提高了时钟频率和吞吐率；对于字节打包环路，通过提取一类可简化电路结构的数据元素，并为之构建快速旁路，增加了环路的处理速度．基于上述方法并辅以基本的电路优化手段，设计实现在现场可编程门阵列（FPGA，Field-Programmable Gate Array）平台上频率可达309MHz，并且每个时钟周期处理一个编码符号．

英文摘要：

To improve the throughput of hardware architecture for CABAC （context-based adaptive binary arithmetic coder）, the optimization methods based on dynamic properties of dataflow were adopted. By building the dataflow model of CABAC algorithm, four inevitable loops brought by hardware implementation were abstracted and isolated, and the potential bottle-neck loops were examined and optimized. For the contextloop, three assistant sub-loops with different iteration cycle were used to update the context variables needed by the data elements with different dependency-cycle. For the byte-package loop, a special kind of data ele- ments was discriminated, which could simplify the circuit architecture and speed up the clock frequency. By building a dedicated fast by-pass channel for these special data elements, the throughput of byte-package loop was improved. Also benefiting from other basic optimization methods, the entire CABAC hardware architecture could achieve 309 MHz on FPGA（field-programmable gate array） platform and process one binary symbol per clock cycle.