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中文摘要：
基于器件物理分析方法，结合高场迁移率、肖特基栅势垒降低、势垒隧穿等物理模型，分析了改进型异质栅结构对深亚微米栅长碳化硅肖特基栅场效应晶体管沟道电势、夹断电压以及栅下电场分布的影响．通过与传统栅结构器件特性的对比表明，异质栅结构在碳化硅肖特基栅场效应晶体管的沟道电势中引入了多阶梯分布，加强了近源端电场；另一方面，相比于双栅器件，改进型异质栅器件沟道最大电势的位置远离源端，因此载流子在沟道中加速更快，在一定程度上屏蔽了漏压引起的电势变化，更好抑制了短沟道效应．此外，研究了不同结构参数的异质栅对短沟道器件特性的影响，获得了优化的设计方案，减小了器件的亚阈值倾斜因子．为发挥碳化硅器件在大功率应用中的优势，设计了非对称异质栅结构，改善了栅电极边缘的电场分布，提高了小栅长器件的耐压．
英文摘要：
Based on the device operation mechanism and physical model, effects of the improved hetero-material-gate （HMG） approach on deep sub-micron silicon carbide （SIC） metal-semiconductor field-effect transistor （MESFET） are analyzed. By comparing with the conventional MESFET, it is shown that the improved HMG approach induces a multi-stepped distribution of the potential in the channel, leading to an enhanced electric field at the source. Meanwhile, the position of the maximum of the channel potential is changed to the drain side compared with the dual-material-gate （DMG） device, thus the carriers in the channel are accelerated more efficiently and the variation of potential caused by drain voltage is eliminated to a certain degree, resulting in a better restraint in short-channel effect. Also, different technological parameters are designed to study the dependence of the device performance and an optimization plan is obtained, leading to a decreased sub-threshold swing. In addition, asymmetric gate structures are designed for high power application, achieving an improved distribution of the electric field at the gate edge and an enhanced breakdown voltage of the small scale device.
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An interconnecting bus power optimization method combining interconnect wire spacing with wire order
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