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中文摘要：
龙芯3号是一款低功耗处理器芯片,要求测试时保持较低功耗.为了解决低功耗测试的问题,对龙芯3号测试功耗进行了细致分析,提出一套考虑测试时间和测试开销的低功耗测试方案,并对整套方案中的各种技术在功耗、面积、时延以及测试时间等方面进行了详细分析.针对龙芯3号测试功耗主要消耗在逻辑电路的翻转和测试时钟网络上的特点,采用IP级测试分割技术减少逻辑电路和时钟网络的翻转;采用门控时钟对局部扫描触发器进行控制减少单核扫描捕获期间的逻辑翻转,并采用了阻隔门技术、不关心位（X位）填充技术减少单核扫描移位的逻辑翻转.实验结果表明,龙芯3号4核处理器达到了预定小于15W的测试平均功耗需求,单个IP核最大平均功耗降低为6W左右,约是正常功能平均功耗的40%,有效地保证了芯片的测试质量.
英文摘要：
To guarantee the test quality,the low-power processor Godson-3 requires low test power.In this paper,based on the detailed analysis of test power consumption,we propose a low power test scheme concerning both test cost and test time.By analyzing the components of test power of the Godson-3,we found that the test power of Godson-3 is mainly contributed by the combinational logics and clock networks.In order to reduce the transitions of combinational logics and clock networks,the IP based test technology and test partitions are used.One IP can be tested separately to target the lower test power,or two identical IP can be tested concurrently to reduce test time.We also use functional clock gating cells,block-gating and X-Filling to further reduce the transitions of single IP.The costs of these technologies including area,delay and test time are analyzed with details.Experimental results show that,the maximum average test power of the single IP is reduced to 6W,which is about 40% of functional average power and can effectively guarantee the test quality.
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