中文摘要：

为了减小电路延迟,提出基于忆阻器蕴含门的逻辑电路综合多阶段进化算法（IMP-ELS）,求得在工作忆阻器数目取不同值的条件下的脉冲数优化电路.将问题建模为等式约束下的最小化问题,当约束违反降低到一定程度时,通过判别当前最优解与待求函数真值表符合的条件,计算与、或、异或三种余项函数之一,将其作为新的待求函数,启动新一轮进化,从而保证得到电路的可行解;设计蕴含门逻辑电路编码及初始化方法,减少随机初始化种群中的非法解和冗余门.对2~11bit标准逻辑函数测试结果表明：当工作忆阻器数目由2增大到3时,该算法对82%的测试函数平均脉冲数降低了28%.

英文摘要：

An evolutionary algorithm for logic synthesis with memristor-based implication gates （IMP ELS） was proposed to minimize the number of pulses under a given number of working mem- ristors. The problem was modeled as a minimization problem with constant constraint. When the constraint violation was decreased to certain degree, one of AND, OR and EXOR remainder functions was obtained through comparing the truth table of the best solution by far and the truth table of the given function. The new evolution process was started to synthesis the obtained remainder function. The multistage evolution could ensure obtaining the feasible solution. A new initialization method was developed to encode the circuit to reduce redundant and illegal gates in initial population. The results on 2-11 bit benchmarks show that the algorithm can decrease pulse numbers by 28% on 82% benchmarks if the number of working memristors is increased from 2 to 3.