传统的栅介质材料SiO2不能满足CMOS晶体管尺度进一步缩小的要求,因此高介电栅介质材料在近几年得到了广泛的研究,进展迅速.本文综述了国内外对高介电材料的研究成果,并结合作者的工作介绍了高介电栅介质在晶化温度、低介电界面层、介电击穿和金属栅电极等方面的最新研究进展.
The traditional gate dielectric material of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.