中文摘要：

三维堆叠集成电路测试中的一个关键的挑战是在功耗约束下,在绑定前测试和绑定后测试中,协同优化测试应用时间和测试硬件开销。将传统的二维芯片的绑定前和绑定后测试调度方法运用于三维堆叠集成电路的测试调度会导致测试应用时间的延长。我们分别针对未堆叠的集成电路和N（N≥2）层芯片堆叠的3D-SICs,提出了一种功耗约束下的测试调度优化算法。在ITC’02基准电路的实验结果表明,算法在功耗约束下,测试应用时间和测试数据寄存器个数分别减少多达33.8%和28.6%,证明算法能有效地权衡测试应用时间和硬件开销。

英文摘要：

A key challenge in 3-Dimension Stacked Integrated Circuits （3D-SICs） testing is to co-optimize the test application time and test hardware overhead in both pre-bond and post-bond test. Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to 3D-SICs, leads to unnecessarily high test application time. In this paper, a test scheduling optimization algorithms for non-stacked Ics and 3D-SICs with an arbitrary number of chips is proposed. The experimental results on the ITC＇02 benchmark circuits show that the test application time and the number of test data register reduces up to 33.8% and 28.6% respectively. It proves that the proposed algorithm can effectively measure the test application time and reduce hardware overhead under power constraints.