中文摘要：

阐述了高速计数器测量陡（快）脉冲上升时间的原理，提出了基于频差倍增技术的计数方案，实现了由较低频率计数器进行较高频率计数，进而提高陡脉冲上升时间测量精度的目的。把高密度可编程逻辑器件（CPLD）的外接100MHz晶振作为系统低频时钟，利用D触发器组对时钟信号进行分频、倒相，经过二级倍频后混频器输出200MHz的脉冲作为计数脉冲，将计数精度提高至5ns左右，满足了测量要求且降低了测量成本，并可推广应用于测量脉冲的下降时间、脉冲宽度和周期等．

英文摘要：

To accurately measure the ascendant time of a high-voltage steep pulse, the pace and precision of counter is highly challenged. The authors put forward the design of high-speed count system based on CPLD and DSP. In this system, the outer crystal oscillator of CPLD act as low-frequency clock whose frequency division and phase invertion are done by D-trigger group designed with CPLD, and finally,they get the counter with 200 MHz i. e. 5ns per period by the method of frequency difference multiply. The counting pace and precision are promoted, and meet the demand to measure the ascendant time of high-voltage steep pulse. It can be extended to measure the descendant time of pulse, pulse width and periods.