中文摘要：

全数字锁相环（ADPLL）在数字通信领域有着极为广泛的应用。由于SoPC技术的发展和FPGA的工作频率与集成度的提高，在1块FPGA芯片上集成整个系统已成为可能。以片内同时嵌入CPU和全数字锁相环为目的，结合现阶段的相关研究成果，简单介绍片内全数字锁相环系统的结构和全数字锁相环的工作原理，详细论述一种可增大全数字锁相环同步范围的数控振荡器的设计方法，并给出部分VHDL设计程序代码和仿真波形。在此数控振荡器的设计中引入翻转触发器的概念，并通过改变翻转触发器的动作特点，使得数控振荡器的输出频率提高，以达到增大全数字锁相环同步范围的目的。

英文摘要：

All Digital Phase- Locked Loop （ADPLL） is generally used in digital communication field. The whole system on chip can be achieved due to development of SoPC and FPGA. Considering the relevant research achievements and the techniques of embedded CPU and ADPLL,the system structure and the principle of ADPLL is introduced in the paper. A design way of a digital control oscillator that will increase synchronous range of ADPLL is discussed in detail,and the partial VHDL code and simulation waveform is given. In this design, toggle flip flop is mentioned. Output frequency of DCO is increased by TFF change. Finally,synchronous range of ADPLL is increased.