中国数字地面电视广播标准采用准循环低密度校验码(QC-LDPC codes)作为其信道编码的内码。根据该类LDPC码的准循环特性,该文提出了一种基于流水线方式的半并行编码结构,可实现发射机中LDPC码的多码率编码;在满足系统净荷数据率的前提下,合理规划多种寄存器,充分复用硬件资源,降低其消耗。使用编程门阵列(FPGA)实现此结构,通过验证,证明了该结构编码结果正确,资源利用率较低。
Quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted as the inner code of channel codes in chinese digital terrestrial television broadcasting standard (CDTTB). These code have encoding advantage over other types of LDPC codes. Based on its systematic circulant form, this paper presents an encoder with semi-parallel and pipeline architectures. The encoding of LDPC codes at multiple rates can be achieved in transmitter. With carefully designing the involved reqisters and fully multiplexing the hardware, resources are reduced on the premises that the payload rates are met. This architecture has been implemented and its functionality verified.