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中文摘要：
针对深亚微米工艺下瞬态故障引发的软错误可能成为芯片失效的重要原因，提出一种容软错误的BIST结构——FT—CBILBO．该结构对并发内建逻辑块观察器进行改进，通过对多输入特征寄存器进行功能复用，构建双模冗余的容错微结构，并且能有效地降低开销；在触发器输出端插入C单元，可有效地针对单事件翻转进行防护，阻塞瞬态故障引发的软错误．在UMC 0．18μm工艺下的实验结果表明，FT—CBILBO面积开销为28．37％～33．29％，性能开销为4．99％～18．20％．
英文摘要：
Soft error caused by transient faults can become an important issue for chip failures under deep sub-micron manufacturing process. This paper proposes a soft-error-tolerant BIST structure, i. e. , FT-CBILBO. As an evolution of CBILBO, FT-CBILBO reuses MISR to construct DMR fault- tolerant scheme to reduce the overhead. FT-CBILBO can block soft error by inserting code word state preserving element to tolerant SEU-induced soft error. The experimental results under UMC 0. 18μm process show that area overhead of FT-CBILBO ranges from 28. 37% to 33. 29%, and performance overhead ranges from 4.99% to 18.20%.
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