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A 5-Gbit／s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS
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  • 相关项目：基于标准CMOS工艺的新型表面超级结射频LDMOS及其模型研究
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基于标准CMOS工艺的新型表面超级结射频LDMOS及其模型研究
期刊论文 48 会议论文 4
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