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中文摘要：
提出了一种在引脚和功耗限制下3DSoCs的绑定前测试方法。对IP核细粒度划分，将每个IP核的触发器数均衡分布到各层芯片上，利用TSV进行互连，设计出一种新颖的三维结构的测试外壳扫描链，同时在功耗和引脚限制下对IP核进行测试调度。实验结果表明，该方法使得芯片的测试时间获得大幅度降低的同时对功耗的需求很小。
英文摘要：
A test method for 3D SoCs under pre-bond test pins and power consumption constraint is presented in this paper. Use fine-granularity partitioning for cores, the number of flip flops in each IP core are partitioned balanced into each layers and interconnected by TSV. A novel 3D IC core wrapper scan-chain is designed and a SoC test scheduling method is proposed under pre-bond test pins and power consumption. Experimental results demonstrate that the test time can be reduced sharply and need less power consumption on 3D SoCs compared to the traditional 2D SoCs.
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