中文摘要：

提出了一种应用于射频接收机自动增益控制（AGC）环路中的10位1 MS/s逐次逼近型模数转换器（SARADC）。动态高精度比较器和自举开关技术应用在设计中,在保证转换速度和精度的同时,降低了电路功耗。芯片采用SMIC 0.13μm 1P8M RF CMOS工艺实现。测试结果表明,在1.2 V电源电压下,采样率为1 MS/s时的芯片功耗（P）仅为148μW。当输入信号频率为101 kHz时,信噪失真比（SNDR）为54 dB,有效位数（ENOB）为8.7 bit,无杂散动态范围（SFDR）为58.1 dB。

英文摘要：

A 10 bit 1 MS/s successive approximation ADC applied in AGC loop of RF receiver is presented.Dynamic high resolution comparator and bootstrap switch are used in the design so as to reduce power.The chip was implemented in SMIC 0.13 μm 1P8M RF CMOS process.Measurement result shows that power dissipation is only 148 μW when conversion speed is 1 MS/s.SNDR is 54 dB,ENOB is 8.7 bit and SFDR is 58.1 dB.